Clock control method and circuit

Details Clock control method and circuit Clock control method and circuit

2007-07-03

2007-07-03

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S407000

Reexamination Certificate

active

11022653

ABSTRACT:
A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

REFERENCES:
patent: 3836887 (1974-09-01), Ueda et al.
patent: 5229667 (1993-07-01), Shimizu
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5319260 (1994-06-01), Wanlass
patent: 5398031 (1995-03-01), Saji
patent: 5469116 (1995-11-01), Slemmer
patent: 5629638 (1997-05-01), Kumar
patent: 5699003 (1997-12-01), Saeki
patent: 5777497 (1998-07-01), Han
patent: 5918202 (1999-06-01), Kuroki et al.
patent: 5923188 (1999-07-01), Kametani et al.
patent: 5939919 (1999-08-01), Proebsting
patent: 6069508 (2000-05-01), Takai
patent: 6075395 (2000-06-01), Saeki
patent: 6084453 (2000-07-01), Fuse et al.
patent: 6100727 (2000-08-01), Nomura
patent: 6104224 (2000-08-01), Koshikawa
patent: 6137336 (2000-10-01), Baba et al.
patent: 6184736 (2001-02-01), Wissell et al.
patent: 6194937 (2001-02-01), Minami
patent: 6222408 (2001-04-01), Saeki
patent: 6307399 (2001-10-01), Lien et al.
patent: 6396320 (2002-05-01), Saeki
patent: 6501316 (2002-12-01), Saeki
patent: 6504414 (2003-01-01), Saeki
patent: 6600354 (2003-07-01), Saeki
patent: 3-104436 (1991-05-01), None
patent: 7-235956 (1995-09-01), None
patent: 8-54957 (1996-02-01), None
patent: 8-137091 (1996-05-01), None
patent: 8-237091 (1996-09-01), None
patent: 10-171548 (1998-06-01), None
patent: 10-256886 (1998-09-01), None
J. Han et al., “Skew Minimization Techniques for 256M-bit Synchronous DRAM and Beyond”, Symposium on VLSI Circuits Digest of Technical Papers (1998), pp. 192-193.
R.B. Watson et al., “Clock Buffer Chip with Absolute Delay Regulation Over Process and Environmental Variations”, Proc. of IEEE, Custom Integrated Circuits Conference (1992), pp. 25.2.1-25.2.5.
Y. Okajima, et al., “Digital Delay Locked Loop and Design Technique for High Speed Synchronous Interface”, IEICE Trans. Electron, vol. E79-C, No. 6, Jun. 1996, pp. 798-807.

Affiliated with

Also associated with

Rating

Clock control method and circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock control method and circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control method and circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3746553