Boots – shoes – and leggings
Patent
1987-09-10
1989-09-19
Malzahn, David H.
Boots, shoes, and leggings
364760, 341 56, G06F 749
Patent
active
048687774
ABSTRACT:
An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.
REFERENCES:
patent: 4646257 (1987-02-01), Essig et al.
Avizienis, "Binary-Compatible Signed-Digit Arithmetic", Proceeding-Fall Joint Computer Conference, 1964, pp. 663-672.
A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi, et al., IECE Japan, vol. 167, D #4, pp. 450-457, 4/84.
A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi, et al. IECE Japan, vol. J66.d, pp. 683-690, 6/84.
A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222, 9/58.
Signed-Digit Number Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers, pp. 389-400, 9/61.
A Class of Binary Divisions Yielding Minimally Represented Quotients Metz IRE Tranactions on Electronic Computers, pp. 761-764, 12/62.
Design of the Arithmetic Units of ILLIAC III, Reduncancy & Higher Radix Methods, Atkins, IEEE Transacts. on Computers, vol. C-19, pp. 720-732, 8/70.
Multiple Operand Addition and Multiplication, Shanker Singh et al., IEEE Transactions on Computers, vol. C-22, No. 2, pp. 113-120.
Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425, 4/76.
Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser, et al. Electronics, pp. 93-99, 9/77.
High Speed Multiplier Using A Redundant Binary Adder tree, Harata, et al. IEEE International Conference on Computer Design, pp. 165-170, 1984.
High Speed VLSI Multiplication Algorithm With A Redundant Binary Addition Tree, Takagi et al., IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795, 9/85.
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu, et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86, 5/87.
Kuninobu Shigeo
Nishiyama Tamotsu
Takagi Naofumi
Malzahn David H.
Matsushita Electric - Industrial Co., Ltd.
LandOfFree
High speed multiplier utilizing signed-digit and carry-save oper does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed multiplier utilizing signed-digit and carry-save oper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed multiplier utilizing signed-digit and carry-save oper will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-374268