System and method for calibrating on-die components

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

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C326S030000

Reexamination Certificate

active

11406947

ABSTRACT:
An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.

REFERENCES:
patent: 2005/0242832 (2005-11-01), Shin
Cox, Dennis T., et al., “VLSI Performance Compensation For Off-Chip Drivers And Clock Generation”, IEEE 1989 Custom Integrated Circuits Conference, CH2671-6/89/0000-0079, pp. 14.3.1-14.3.4.
Fan, Yongping et al., “On-Die Termination Resistors With Analog Impedance Control For Standard CMOS Technology”, IEEE Journal of Solid-State Circuits, vol. 38, No. 2, (Feb. 2003), pp. 361-364.
Gabara, Thaddeus, et al., “Ground Bounce Control In CMOS Integrated Circuits”, Digest of Technical Papers, IEEE Int'l Solid State Circuits Conference, ISCC 88 (Feb. 1988), pp. 88-90.
Lim, Chee How et al., “Output Buffer With Self-Adjusting Slew Rate And On-Chip Compensation”, Paper from Portland Technology Development, Intel Coporation and Dept. of Electrical Engineering, Portland State Universary, pp. 1-5, Feb. 2-3, 1998.
Song, Ho Young, et al., “A 1.2Gb/S/pin Double Data Rate SDRAM With On-Die-Termination”, IEEE Int'l Solid-State Circuits Conference, ISSCC (Feb. 2003), Paper 17.8, pp. 1-10.
Yoo, C., et al., “A 1.8V 700 Mb/s/pin 512 Mb DDR-II SDRAM With On-Die Termination And Off-Chip Driver Calibration”, IEEE Int'l Solid State Circuits Conference, ISSCC (Feb. 2003), Paper 17.7, pp. 1-15.

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