High throughput AES architecture

Details High throughput AES architecture High throughput AES architecture

2007-05-22

2007-05-22

Vu, Kim (Department: 2135)

Cryptography

Key management

C380S028000, C380S037000

Reexamination Certificate

active

10132788

ABSTRACT:
An advanced encryption system (AES) architecture includes a maximum parallel encryption module which implements one round of the AES algorithm in one clock cycle, and a maximum parallel key scheduling module which generates sub-keys in one clock cycle in parallel with the encryption module, thereby permitting feedback modes of operation to be used without adversely affecting AES throughput. A controller controls the operation of the encryption and key scheduling modules such that one round is completed per clock cycle. The controller is preferably part of a hierarchical distributed control scheme comprising communicating finite state machines (FSMs). The architecture also preferably includes asynchronous input and output buffers.

REFERENCES:
patent: 4514803 (1985-04-01), Agnew et al.
patent: 5748741 (1998-05-01), Johnson et al.
patent: 6026490 (2000-02-01), Johns-Vano et al.
patent: 6937727 (2005-08-01), Yup et al.
patent: 2002/0048364 (2002-04-01), Gligor et al.
patent: 2002/0108048 (2002-08-01), Qi et al.
patent: 2002/0131588 (2002-09-01), Yang
patent: 2002/0191784 (2002-12-01), Yup et al.
patent: 2003/0053623 (2003-03-01), McCanny et al.
patent: 2003/0068036 (2003-04-01), Macchetti et al.
Wayne Wolf, “Computers Components Principles of Embedded Computing System Design”, Academic Press, 2001, p. 99.
Trichina et al, “Supplement Cryptographic Hardware for Smart Cards”, IEEE, Nov.-Dec. 2001, p. 26-35.
Hardware Evaluation of the AES Finalists, Ichikawa et al., The Third Advanced Encryption Standard Candidate Conference, Apr. 13-14, 2000, New York.
An FPGA Implementation and Performance Evaluation of the AES Bloods Cipher Candidate Algorithm Finalists, Elbirt et al., The Third Advanced Encryption Standard Candidate Conference, Apr. 13-14, 2000, New York, pp. 1-15.

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