Multilayer interconnection structure of a semiconductor

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S758000, C257S762000, C257S767000, C257S771000, C257S774000, C257S775000

Reexamination Certificate

active

09225351

ABSTRACT:
In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

REFERENCES:
patent: 5459353 (1995-10-01), Kanazawa
patent: 5763954 (1998-06-01), Hyakutake
patent: 5895265 (1999-04-01), Inoue et al.
patent: 405152445 (1993-06-01), None
patent: 409219381 (1997-08-01), None
C-K, Hu et al., “Electromigration in two-level interconnect structures with Al alloy lines and W studs,” J. Appl. Phys. 72 (1), Jul. 1, 1992, pp. 291-293.

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