Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-07-31

2007-07-31

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S189080

Reexamination Certificate

active

11400404

ABSTRACT:
A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray12includes a first MOS transistor PD1for charging a main bit line MBL1and a second MOS transistor PS1for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1is connected to a power source voltage, and the source electrode of the first MOS transistor PD1is connected via a fourth MOS transistor PD2to the power source voltage. Since there is not a resistance between the main bit line MBL1and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

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