High-speed parallel-prefix modulo 2n-1 adders

Details High-speed parallel-prefix modulo 2n-1 adders High-speed parallel-prefix modulo 2n-1 adders

2006-12-26

2006-12-26

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S490000

Reexamination Certificate

active

07155473

ABSTRACT:
A parallel-prefix modulo 2n−1 adder that is as fast as the fastest parallel prefix 2ninteger adders, does not require an extra level of logic to generate the carry values, and has a very regular structure to which pipeline registers can easily be added. All nodes of the adder have a fanout ≦2. In the prefix structure of the adder, each carry value term output by the parallel prefix structure is determined by the all of the bits in the operands input to the adder. In one embodiment, there are log2n stages in the prefix structure. Each stage has n logical operators, and all of the logical operators in the prefix structure are of the same kind. Pipeline registers may be inserted before and/or after a stage in the prefix structure.

REFERENCES:
patent: 3925652 (1975-12-01), Miller
patent: 4598266 (1986-07-01), Bernardson

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