Type-II all-digital phase-locked loop (PLL)

Details Type-II all-digital phase-locked loop (PLL) Type-II all-digital phase-locked loop (PLL)

2006-12-05

2006-12-05

Cheng, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000, C331S00100A, C375S376000, C375S327000

Reexamination Certificate

active

07145399

ABSTRACT:
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit1115) and an integral loop gain block (integral loop gain block1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

REFERENCES:
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patent: 6018556 (2000-01-01), Janesch et al.
patent: 6809598 (2004-10-01), Staszewski et al.
patent: 2001/0005164 (2001-06-01), Okamoto
patent: 0 590 323 (1994-04-01), None
patent: 1 217 745 (2002-06-01), None
“All Digital Phase-Locked Loop: Concepts, Design and Applications”, Y. R. Shayan and T. Le-Ngoc, IEEE Proceedings F. Communications, Radar & Signal Processing, Institution of Electrical Engineers. Stevenage, GB, vol. 138, No. 1, Part F, Feb. 1, 1989, pp. 53-58.

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