Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-12-05
2006-12-05
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185270
Reexamination Certificate
active
07145808
ABSTRACT:
A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2ato9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
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Fujiwara Ichiro
Nobukata Hiromi
Kananen Ronald P.
Nguyen Tan T.
Rader Fishman & Grauer
Sony Corporation
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