Semiconductor memory

Details Semiconductor memory Semiconductor memory

2006-02-21

2006-02-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050

Reexamination Certificate

active

07002875

ABSTRACT:
A latch signal generator generates a latch signal in synchronization with later one of a timing at which a delayed chip enable signal obtained by delaying a chip enable signal is activated and a transition timing of a clock signal. A latch circuit latches an input signal received by a signal input buffer, in synchronization with the latch signal. By changing the timing the latch signal is generated in accordance with set-up time of the input signal with respect to the clock signal, it is possible to reduce the stand-by current and prevent malfunction of a semiconductor memory caused by improper latch of the input signal.

REFERENCES:
patent: 6249483 (2001-06-01), Kim
patent: 6256260 (2001-07-01), Shim et al.
patent: 6385127 (2002-05-01), Ikeda
patent: 10-55665 (1998-02-01), None

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