Memory array including multiple-gate charge trapping...

Details Memory array including multiple-gate charge trapping... Memory array including multiple-gate charge trapping...

2006-10-10

2006-10-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185100, C365S185260

Reexamination Certificate

active

07120059

ABSTRACT:
An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath each of all or some of the gates in the plurality of gates. Word lines and bit lines source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates. Sector select lines are included to couple selected sectors to the bit lines.

REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5270969 (1993-12-01), Iwahashi
patent: 5278439 (1994-01-01), Ma et al.
patent: 5408115 (1995-04-01), Chang
patent: 5448517 (1995-09-01), Iwahashi
patent: 5515324 (1996-05-01), Tanaka
patent: 5753950 (1998-05-01), Kojima
patent: 5768192 (1998-06-01), Eitan
patent: RE35838 (1998-07-01), Momodomi et al.
patent: 5793677 (1998-08-01), Hu et al.
patent: 5877054 (1999-03-01), Yamauchi
patent: 5895949 (1999-04-01), Endoh
patent: 6011725 (2000-01-01), Eitan
patent: 6096603 (2000-08-01), Chang et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6194272 (2001-02-01), Sung
patent: 6522585 (2003-02-01), Pasternak
patent: 6552386 (2003-04-01), Wu
patent: 6614070 (2003-09-01), Hirose et al.
patent: 6645813 (2003-11-01), Hsieh
patent: 6657894 (2003-12-01), Yeh et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 6670671 (2003-12-01), Sasago et al.
patent: 6690601 (2004-02-01), Yeh et al.
patent: 6714457 (2004-03-01), Hsu et al.
patent: 6798012 (2004-09-01), Ma et al.
patent: 6856551 (2005-02-01), Mokhlesi et al.
patent: 6885044 (2005-04-01), Ding
patent: 6933555 (2005-08-01), Hsieh
patent: 7009882 (2006-03-01), Chen
patent: 7018895 (2006-03-01), Ding
patent: 2004/0084714 (2004-05-01), Ishii et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2005/0001258 (2005-01-01), Forbes
patent: 2006/0044872 (2006-03-01), Nazarian
Lahiri, S. K., “MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMS: A New Concept”, Physics of Semiconductor Devices, Dec. 1997, pp. 951-956, vol. 3316, No. 2.
Lee, Jae-Duk, et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, 264-266.
Shin, Yoocheol, et al., “High Reliable SONOS-type NAND Flash Memory Cell with AI2O3 for Top Oxide,” Non-Volatile Semiconductor Memory Workshop, 2003, 2 pages.
Naruke, K., et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side,” IEDM Tech. Dig. 1989, 603-606.
U.S. Appl. No. 10/855,286, filed May 26, 2004, “Nand-Type Non-Volatile Memory Cell and Method for Operating Same,” 51 pages.
Lung, Hsiang Lan, “Inversion Bit Line, Charge Trapping Non-Volatile Memory and Method of Operating Same,” U.S. Appl. No. 11/118,839, filed Apr. 29, 2005, 34 pages.
U.S. Appl. No. 11/085,458, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Gate-by-Gate Erase for Same,” 73 pages.
U.S. Appl. No. 11/085,326, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory with Two Trapping Locations Per Gate, and Method for Operating Same,” 73 pages.
U.S. Appl. No. 11/085,300, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Operating Same,” 73 pages.
U.S. Appl. No. 11/085,444, filed Mar. 21, 2005, entitled “Method for Manufacturing a Multiple-Gate Charge Trapping Non-Volatile Memory,” 71 pages.
Fujiwara, I., et al., “0.13 μm MONOS single transistor memory cell with separated source lines,” IEDM 1998, 995-998.
Kobayashi, T., et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEDM 2001, 2.2.1-2.2.4.
Lung, Hsiang Lan, U.S. Appl. No. 11/118,839, filed Apr. 29, 2005, “Inversion Bit Line, Charge Trapping Non-Volatile Memory and Method of Operating Same”, 34 pages.
Chang, Kuo-Tung, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, 253-255.
Eitan, Boaz, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, 543-545.
Sasago, Y, et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10 MB/s,” IEEE, 2003, 4 pages.

Affiliated with

Also associated with

Rating

Memory array including multiple-gate charge trapping... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory array including multiple-gate charge trapping..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array including multiple-gate charge trapping... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3709834