Mechanism to eliminate the performance penalty of computed jump

Details Mechanism to eliminate the performance penalty of computed jump Mechanism to eliminate the performance penalty of computed jump

1997-06-23

2000-03-07

Lall, Parshotam S.

G06F 932

Patent

active

060351187

ABSTRACT:
A technique for eliminating the performance penalty of implementing jump instructions in a deeply pipelined processor includes a pipeline having a signal for indicating that the top of the address return stack has been updated by an address moved to the return register. An instruction moving a previously computed jump target address to the return register is included in code to be executed. The pipeline uses the instruction at the top of the RAS as a guess of the target instruction of a fetched jump instruction and immediately begins fetching instructions indicated by the guess.

REFERENCES:
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5526498 (1996-06-01), Matsuo et al.
patent: 5623614 (1997-04-01), Van Dyke et al.
patent: 5706491 (1998-01-01), McMahan
Daniel Tabak, "The Sun Sparc," RISC Systems, pp. 144-161, Research Studies Press Ltd., Somerset, England and John Wiley & Sons, Inc., New York, Chichester, Toronto, Brisbane, Singapore.

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