Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-08-29
2006-08-29
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185110
Reexamination Certificate
active
07099200
ABSTRACT:
In a 3Tr. NAND including a cell unit constituted of one memory cell and two select gate transistors between which the cell is held, to renew data by a byte unit, at an erase time, a potential of a bit line or source line can be set by the byte unit, so that erase by the byte unit is possible. Accordingly, with respect to only the data of the memory cell which is a renewal object, an erase/write operation is performed, and reliability of a memory operation is enhanced.
REFERENCES:
patent: 4636984 (1987-01-01), Neukomm
patent: 5777925 (1998-07-01), Tokushige
patent: 5949714 (1999-09-01), Hemink et al.
patent: 6307807 (2001-10-01), Sakui et al.
patent: 6370081 (2002-04-01), Sakui et al.
patent: 6512703 (2003-01-01), Sakui et al.
patent: 6862223 (2005-03-01), Lee et al.
patent: 2001/0017789 (2001-08-01), Noda
patent: 2001/0050377 (2001-12-01), Ikehashi et al.
patent: 0 986 067 (2000-03-01), None
patent: 8-87895 (1996-04-01), None
patent: 11-195718 (1999-07-01), None
patent: 11-297081 (1999-10-01), None
patent: 2000-149581 (2000-05-01), None
patent: 2002-43444 (2002-02-01), None
patent: 10-0207972 (1999-07-01), None
patent: 2000-0023005 (2000-04-01), None
Art Lancaster, et al. “A 5V-Only EEPROM with Internal Program/Erase Control”, ISSCC Digest of Technical Papers, 1983 IEEE International Solid-State Circuits Conference, Session XIII: Nonvolatile Memory, Feb. 24, 1983, p. 164-165 and p. 302.
Fujio Masuoka, et al., “New Ultra High Density EPROM and Flash EEPROM with NAND Structure Cell”, IEDM 87, pp. 552-555.
Fujio Masuoka, et al., “A New Flash E2PROM Cell Using Triple Polysilicon Technology”, IEDM 84, pp. 464-467.
William S. Johnson, et al. “A 16Kb Electrically Erasable Nonvolatile Memory” Digest of Technical Papers, 1980 IEEE International Solid-State Circuits Conference, Session XII: ROMs, PROMs and EROMs, Feb. 14, 1980, p. 152-153 and p. 271.
U.S. Appl. No. 11/083,156, filed Mar. 18, 2005, Hasegawa et al.
Hoang Huan
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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