Method for performing simulation of a semiconductor integrated c

Details Method for performing simulation of a semiconductor integrated c Method for performing simulation of a semiconductor integrated c

1998-02-25

2000-03-07

Teska, Kevin J.

G06F 9455

Patent

active

060351152

ABSTRACT:
A method for performing simulation of a semiconductor integrated circuit is disclosed in which a circuit simulation result taking into consideration can be obtained relative variation. In the method, possible maximum and minimum values of an element parameter, i.e., element parameters of a worst case taking into consideration the relative variation is determined from prescribed absolute and relative variation ranges to form a variation model. Based on the variation model, worst-case simulation is carried out taking into account the relative variation.

REFERENCES:
patent: 4744084 (1988-05-01), Beck et al.
patent: 5590063 (1996-12-01), Golio et al.
patent: 5621652 (1997-04-01), Eakin
patent: 5692160 (1997-11-01), Sarin

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