Delay locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S047000

Reexamination Certificate

active

07061287

ABSTRACT:
Provided is a delay locked loop comprising: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase detector for generating a signal for controlling the delay amount of the delay unit comparing the clock supplied from the external chipset with a phase of an output of the replica, and generating a reset signal through detection of a change of a clock frequency supplied from the external chipset.

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