Integrated circuit with reduced analog coupling noise

Details Integrated circuit with reduced analog coupling noise Integrated circuit with reduced analog coupling noise

2006-08-01

2006-08-01

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S203000

Reexamination Certificate

active

07084439

ABSTRACT:
In order for circuit blocks1to3composed by the CMOS process, and analog lines5-1, 5-2, and5-3connected thereto not to overlap on the layout, the analog lines5-1and5-2are wired so that such lines roundabout the layout of the AM/FM common circuit block3. Through this, the distance of the signal line within the AM/FM common circuit block3and the analog lines5-1and5-2can become as long as possible, the signal line within the AM/FM common circuit block3and the analog lines5-1and5-2would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines5-1and5-2can be suppressed.

REFERENCES:
patent: 04-080946 (1992-03-01), None
patent: 04-296918 (1992-10-01), None
patent: 05-047943 (1993-02-01), None
patent: 09-160684 (1997-06-01), None
patent: 2000-101021 (2000-04-01), None
patent: 2001-069128 (2001-03-01), None
“Multiple Twisted Dataline Techniques for Multigigabit DRAM's”, Dong-Sun Min and Dietrich W. Langer, IEEE Journal of Solid-State Circuits, vol. 34, No. 6, pp. 856-865, Jun. 1999.

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