Nonvolatile semiconductor memory device and method of...

Details Nonvolatile semiconductor memory device and method of... Nonvolatile semiconductor memory device and method of...

2006-10-03

2006-10-03

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185240

Reexamination Certificate

active

07116581

ABSTRACT:
A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.

REFERENCES:
patent: 5751637 (1998-05-01), Chen et al.
patent: 6801457 (2004-10-01), Tanzawa et al.
patent: 2001-357693 (2001-12-01), None

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