Circuit for detecting a center level of a FSK demodulated...

Details Circuit for detecting a center level of a FSK demodulated... Circuit for detecting a center level of a FSK demodulated...

2006-08-08

2006-08-08

Tran, Khanh (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C329S300000

Reexamination Certificate

active

07088790

ABSTRACT:
In demodulation of a FSK signal, a circuit for detecting a center level of said signal and correcting an error thereof is provided. Said circuit can accomplish the detection of the center level correctly always even if there exist cords with various lengths in a length of “1” or “0” of a synchronizing signal at beginning of communication and during communication, and yet frequency variation happens at that time.Said circuit has sample hold circuits SH1and SH2each of which are provided so as to correspond to “1” and “0” of an input demodulated data signal. In said circuit a center level value is an average value of voltages held in said sample hold circuits when said signal changes from “1” to “0” or “0” to “1” and a center level value is obtained by adding or subtracting a voltage of ½ of difference between two hold voltages held in another sample hold circuit SH3to or from a hold voltage in a receiving side at present time when said signal keeps “1” or “0” continuously.Data information is judged by a compartor of which a reference value is anyone of said two center level value.

REFERENCES:
patent: 5111152 (1992-05-01), Makino
patent: 6122330 (2000-09-01), Motohashi
patent: 6188733 (2001-02-01), Kawai
patent: 6529565 (2003-03-01), Kawai
patent: 6570937 (2003-05-01), Kawai
patent: 6633752 (2003-10-01), Hashigaya
patent: 6891905 (2005-05-01), Malone et al.

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