Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2006-11-21
2006-11-21
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S158000
Reexamination Certificate
active
07138845
ABSTRACT:
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback signal in controlling coarse phase adjustment signals indicating whether a delay of a coarse delay line should be increased or decreased. Similarly, a fine phase detector compares the reference signal and feedback signal to generate a locking bias signal, which may increase or decrease a delay of an analog fine delay line. The analog fine delay line and coarse delay line may be connected in series creating the hybrid delay line having a total delay comprised of the coarse delay and the fine delay. Additionally, a fine bias generator may control the fine delay in response to an initiating bias signal from an analog phase generator or the locking bias signal.
REFERENCES:
patent: 6100735 (2000-08-01), Lu
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6242955 (2001-06-01), Shen et al.
patent: 6282253 (2001-08-01), Fahrenbruch
patent: 6392456 (2002-05-01), Pyeon et al.
patent: 6445231 (2002-09-01), Baker et al.
patent: 6518807 (2003-02-01), Cho
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6559699 (2003-05-01), Lee et al.
patent: 6628154 (2003-09-01), Fiscus
patent: 6731147 (2004-05-01), Fiscus
patent: 6765976 (2004-07-01), Oh
patent: 6868504 (2005-03-01), Lin
patent: 6937076 (2005-08-01), Gomm
patent: 2002/0101292 (2002-08-01), Maneatis
patent: 2002/0172314 (2002-11-01), Lin et al.
patent: 2004/0125905 (2004-07-01), Vlasenko et al.
patent: 1 282 229 (2003-02-01), None
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Moon et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000, pp. 377-384.
International Search Report dated Nov. 2, 2005 (4 pages).
Written Opinion of the International Searching Authority dated Nov. 2, 2005 (7 pages).
Callahan Timothy P.
Cox Cassandra
Micro)n Technology, Inc.
TraskBritt
LandOfFree
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