Method to etch poly Si gate stacks with raised STI structure

Details Method to etch poly Si gate stacks with raised STI structure Method to etch poly Si gate stacks with raised STI structure

2006-12-26

2006-12-26

Norton, Nadine (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S248000, C438S257000, C438S259000, C438S391000, C257SE21206, C257SE21628

Reexamination Certificate

active

07153781

ABSTRACT:
In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising:a) etching a gate silicide layer+a poly Si 2 layer;b) forming a continuous poly Si passivation layer on sidewalls of the silicide and poly Si 2 layers and at the interface of the poly Si 2 layer and a poly Si 1 layer and affecting thermal oxidation to form an underlying thin Si oxide gate layer;c) affecting a Si oxide breakthrough etch to clear the passivation layer at interface of the poly Si 2 and the poly Si 1 layers while leaving intact the passivation layer on the sidewalls of the silicide and the poly Si 2 layers; andd) etching the poly Si 1 layer with an oxide selective process to preserve the underlying thin gate oxide and thin passivation layer at the sidewall to obtain vertical profiles of poly Si gate stacks both at the AA and the STI oxide.

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