Extended address translation system for pointer updating in page

Details Extended address translation system for pointer updating in page Extended address translation system for pointer updating in page

1994-06-14

1995-05-30

Harvey, Jack B.

G06F 1210

Patent

active

054209935

ABSTRACT:
A system for updating logical address data in pointers used by a processor in a computer system using paged memory. An Actual Segment Descriptor Associative Memory System (ASDAM) provides a dual cache memory for searching page table logical addresses and page index values which can, if available, provide a logical address, via a logical address RAM, to update a pointer in one machine cycle, with a new logical address. If the required data is not available in the dual cache memory, then other circuitry is operative to translate logical addresses into physical addresses permitting rapid access to main memory in order to supply the dual cache memory and logical address RAM with the required data.

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Hayes, John P. Computer Architecture and Organization McGraw-Hill, 1978, pp. 370-375.

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