Method and apparatus for providing efficient software debugging

Details Method and apparatus for providing efficient software debugging Method and apparatus for providing efficient software debugging

1995-06-19

1997-04-15

Beausoliel, Jr., Robert W.

Boots, shoes, and leggings

395568, 395591, 364267, 36426791, 3642755, 364DIG1, G06F 1100

Patent

active

056218869

ABSTRACT:
A method and apparatus for the separate enablement of debug events during the execution of operating system routines and non-operating system routines. According to one aspect of the invention, a processor is described which may operate in a first mode and a second mode. While operating in the first mode, the processor allows for access to additional resources which are not available in the second mode. The processor generally includes a first storage area, a circuit, and debug circuitry. The first storage area has stored therein a first indication. This first indication indicates which mode the processor is currently operating in. The circuit has stored therein a second indication and a third indication. The second indication indicates whether a debug event is to be recognized while the processor is operating in the first mode. The third indication indicates whether the debug event is to be recognized while the processor is operating in the second mode. The debug circuitry is coupled to the first storage area to receive the first indication. The debug circuitry is also coupled to the circuit to receive either the second indication or the third indication based on the state of the first indication. The debug circuitry allows for the recognition of the debug event based on the state of the indication it receives from the circuit.

REFERENCES:
patent: 4176394 (1979-11-01), Kaminski et al.
patent: 4179734 (1979-12-01), O'Leary
patent: 4279016 (1981-07-01), Leininger et al.
patent: 4306287 (1981-12-01), Huang
patent: 4403284 (1983-09-01), Sacarisen et al.
patent: 4409654 (1983-10-01), Wada et al.
patent: 4488227 (1984-12-01), Miu et al.
patent: 4598364 (1986-07-01), Gum et al.
patent: 4709324 (1987-11-01), Kloker
patent: 4725947 (1988-02-01), Shonai et al.
patent: 4755997 (1988-07-01), Takahashi
patent: 4783731 (1988-11-01), Miyazaki et al.
patent: 4924382 (1990-05-01), Shouda
patent: 5095426 (1992-03-01), Senta
patent: 5197138 (1993-03-01), Hobbs et al.
patent: 5237666 (1993-08-01), Suzuki et al.
patent: 5249278 (1993-09-01), Krauskopf
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5319763 (1994-06-01), Ho et al.
patent: 5341500 (1994-08-01), Moyer et al.
patent: 5361348 (1994-11-01), Nakamoto
patent: 5367550 (1994-11-01), Ishida
patent: 5371894 (1994-12-01), Di Brino
patent: 5379301 (1995-01-01), Sato et al.
patent: 5386519 (1995-01-01), Nakamura et al.
patent: 5448705 (1995-09-01), Nguyen et al.
patent: 5493664 (1996-02-01), Doi
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5533192 (1996-07-01), Hawley et al.
patent: 5564028 (1996-10-01), Swoboda et al.
Pentium.TM. Processor User's Manual, vol. 3: Architecture and Programming Manual, Intel Corporation 1994, pp. 14-1-14-27 and 17-1-17-9.
Intel 80960KB Programmer's Reference Manual, Intel Corporation 1988, pp. 10-1-10-8.

Affiliated with

Also associated with

Rating

Method and apparatus for providing efficient software debugging does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for providing efficient software debugging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing efficient software debugging will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-369033