Method of making sacrificial self-aligned interconnection...

Details Method of making sacrificial self-aligned interconnection... Method of making sacrificial self-aligned interconnection...

2006-02-07

2006-02-07

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000, C438S221000, C438S296000, C438S586000, C438S597000

Reexamination Certificate

active

06995072

ABSTRACT:
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

REFERENCES:
patent: 4786954 (1988-11-01), Morie et al.
patent: 4855952 (1989-08-01), Kiyosumi
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5120677 (1992-06-01), Wakamatsu
patent: 5166084 (1992-11-01), Pfiester
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5343354 (1994-08-01), Lee et al.
patent: 5389559 (1995-02-01), Hsieh et al.
patent: 5395786 (1995-03-01), Hsu et al.
patent: 5429978 (1995-07-01), Lu et al.
patent: 5594682 (1997-01-01), Lu et al.
patent: 5763931 (1998-06-01), Sygiyama
patent: 5795804 (1998-08-01), Jenq
patent: 5811283 (1998-09-01), Sun
patent: 5827765 (1998-10-01), Stengl et al.
patent: 5981330 (1999-11-01), Jenq
patent: 6168986 (2001-01-01), Walker et al.
Nesbit et al., “A 0.6 um2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)”, IEDM 93-627, pp. 26.2.1-26.2.4, 0-7803-1450-6 1993 IEEE.

Affiliated with

Also associated with

Rating

Method of making sacrificial self-aligned interconnection... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making sacrificial self-aligned interconnection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making sacrificial self-aligned interconnection... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3686076