Semiconductor wafer test system

Details Semiconductor wafer test system Semiconductor wafer test system

2006-12-19

2006-12-19

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C257SE21521, C257SE21531

Reexamination Certificate

active

07151003

ABSTRACT:
A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no break-down occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.

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