Cipher block chaining mode in encryption/decryption processing

Cryptography – Particular algorithmic function encoding – Nbs/des algorithm

Reexamination Certificate

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Details

C380S037000, C380S043000

Reexamination Certificate

active

07006627

ABSTRACT:
A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.

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XILINX, “Virtex™ -II, Platform FPGAs: Detailed Description,” DS031-2 (v2.1.2), p. 14, May 7, 2003.

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