Method of operating a data processing apparatus to compute corre

Details Method of operating a data processing apparatus to compute corre Method of operating a data processing apparatus to compute corre

1993-11-30

1995-05-30

Mai, Tan V.

Boots, shoes, and leggings

364734, G06F 700, G06F 738

Patent

active

054208092

ABSTRACT:
A method of computing a mean squared error between a predetermined plural number of pairs of first and second values employs a data processing apparatus (71, 72, 73, 74) having data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. A status detector determines whether the result is less than zero. The flags register (211) stores status bits indicating this detected status. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum. In an alternative embodiment, the arithmetic logic unit can perform operations upon data in separate sections. The arithmetic logic unit makes plural simultaneous subtractions and forms plural status bits for corresponding sections. These plural status bits controls the absolute value function by conditional addition or subtraction of each section. The multiplication unit may also support multiplication byplural sections. The result is a single data word with plural products. The plural products are added to respective running sums using sections of the arithmetic logic unit. The final separate running sums are added to form the general sum.

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