Method and apparatus for testing semiconductor integrated circui

Details Method and apparatus for testing semiconductor integrated circui Method and apparatus for testing semiconductor integrated circui

1995-06-07

1997-04-15

Beausoliel, Jr., Robert W.

Excavating

371 221, G01R 3130

Patent

active

056217420

ABSTRACT:
A method and apparatus for testing a semiconductor integrated circuit device is described. During an aging test of the integrated circuit device, a situation, in which latch up of the semiconductor integrated circuit device can occur, is intermittently created by intermittently supplying a pulse of a power supply voltage V.sub.b, which is higher than a normal voltage V.sub.a in accordance with a rated power supply voltage of the tested integrated circuit device. The power supply to the tested semiconductor integrated circuit device is temporarily cut off when latch up occurs. If a second latch up occurs after a restart of the aging test, it is determined that there is an abnormality in the tested semiconductor integrated circuit device. The power supply to the tested semiconductor integrated circuit device is permanently cut off in response to this determination. This prevents damage to the test-object integrated semiconductor device and permits later determination of the degree to which the device is latch up immune.

REFERENCES:
patent: 4827208 (1989-05-01), Oliver et al.
patent: 5025344 (1991-06-01), Maly et al.
patent: 5107523 (1992-04-01), Heany et al.
patent: 5161161 (1992-11-01), Malek-Khosravi et al.
patent: 5265099 (1993-11-01), Feinstein
Menozzi et al "An Improved Procedure to Test CMOS ICs for Latch Up" 1990 Int. Test Conference IEEE pp. 1028-1034.
Hidaka et al., "A 34ns 16-Mb DRAM wim Controllable Voltage Down-Converter" IEEE Journal of Solid State Electronics 1992 pp. 1020-1027.
Mammano et al. "A New Linear Regulator Features Switch Mode Over Current Protection" APEC 4th Annual Conf. 1989 IEEE pp. 159-164.

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