Process for making a memory structure

Details Process for making a memory structure Process for making a memory structure

2006-11-21

2006-11-21

Everhart, Caridad (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S737000, C438S713000, C257SE21033, C257SE21035

Reexamination Certificate

active

07138341

ABSTRACT:
An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.

REFERENCES:
patent: 5529952 (1996-06-01), Smith et al.
Shoji et al., “All Refractory Josephson Tunnel Junctions Fabricated by Reactive Ion Etch,” IEEE 1983, pp. 827-830.

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