Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-11-21
2006-11-21
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S738000, C438S740000, C257SE21252, C257SE21507, C257SE21583
Reexamination Certificate
active
07138340
ABSTRACT:
Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.
REFERENCES:
patent: 6342449 (2002-01-01), Miyakawa
patent: 6562714 (2003-05-01), Lee
patent: 6635576 (2003-10-01), Liu et al.
patent: 2002/0110966 (2002-08-01), Lee
Jung Tae-Woo
Lee Sung-Kwon
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Ghyka Alexander
Hynix / Semiconductor Inc.
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