Method for configuring multiple-output phase-locked loop...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S147000

Reexamination Certificate

active

07132864

ABSTRACT:
A method is provided to configure a multiple-output phase-locked loop frequency synthesizer based upon a desired set of output frequencies. The method includes an act of selecting a candidate output frequency(s) for the synthesizer's VCO and corresponding configurations for the output dividers. Based upon the candidate output frequency(s) and corresponding output divider configurations, the method provides another act of selecting a suitable feedback signal and input and feedback divider configurations. The resulting various potential configurations for the frequency synthesizer are tested based upon predetermined suitable criteria to provide a selected frequency synthesizer configuration.

REFERENCES:
patent: 5986485 (1999-11-01), O'Sullivan
patent: 6542040 (2003-04-01), Lesea
patent: 6608530 (2003-08-01), Green et al.
patent: 2002/0190764 (2002-12-01), Nichols
“Software Download: RoboConfig 1.0”, Cypress Semiconductor Corporation, copyright 1995-2003.
“High-Speed Multi-Phase PLL Clock Buffer”, Cypress Semiconductor Corporation, Jul. 25, 2003.

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