Semiconductor memory and method of manufacturing the same

Details Semiconductor memory and method of manufacturing the same Semiconductor memory and method of manufacturing the same

1986-11-18

1988-11-29

James, Andrew J.

H01L 2978

Patent

active

047885807

ABSTRACT:
A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.

REFERENCES:
patent: 4328611 (1982-05-01), Harrington
IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 940-942, New York, G. A. Sai-Halasz et al: "Bipolar dynamic RAM cell structure with low soft-error rate".
"Building a dynamic RAM with SMOS", Electronic Design, Mar. 18, 1982, p. 233.

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