Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2006-06-13
2006-06-13
Richards, N. Drew (Department: 2815)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S250000, C438S253000, C438S393000, C438S396000, C438S397000
Reexamination Certificate
active
07060584
ABSTRACT:
A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer which, in a second step, is then etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.
REFERENCES:
patent: 4240196 (1980-12-01), Jacobs et al.
patent: 4966864 (1990-10-01), Pfiester
patent: 5005103 (1991-04-01), Kwon et al.
patent: 5068697 (1991-11-01), Noda et al.
patent: 5356826 (1994-10-01), Natsume
patent: 5371700 (1994-12-01), Hamada
patent: 5374578 (1994-12-01), Patel et al.
patent: 5397729 (1995-03-01), Kayanuma et al.
patent: 5447879 (1995-09-01), Park
patent: 5470775 (1995-11-01), Nariani
patent: 5482894 (1996-01-01), Havemann
patent: 5545585 (1996-08-01), Wang et al.
patent: 5618749 (1997-04-01), Takahashi et al.
patent: 5683931 (1997-11-01), Takahashi
patent: 5728619 (1998-03-01), Tsai et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5918119 (1999-06-01), Huang
patent: 5918147 (1999-06-01), Filipiak et al.
patent: 5929473 (1999-07-01), Nishihori et al.
patent: 5986318 (1999-11-01), Kim et al.
patent: 6083785 (2000-07-01), Segawa et al.
patent: 6083804 (2000-07-01), Chuang
patent: 6090656 (2000-07-01), Randazzo
patent: 6107136 (2000-08-01), Melnick et al.
patent: 6200846 (2001-03-01), Watanabe
patent: 6208033 (2001-03-01), Doan et al.
patent: 6225658 (2001-05-01), Watanabe
patent: 06318673 (1994-11-01), None
patent: 08076940 (1996-10-01), None
patent: 09036313 (1997-02-01), None
patent: 10004179 (1998-01-01), None
patent: 411307722 (1999-11-01), None
Bencher et al., “Dielectric Antireflective Coatings for DUV Lithography”, Solid State Technology, Mar. 97, vol. 40, issue 3.
Carns Timothy K.
DeBruler Lee J.
Horvath John L.
Westphal Michael J.
Richards N. Drew
Silicon Edge Law Group LLP
Wallace Darien K.
Wallace T. Lester
ZiLOG, Inc.
LandOfFree
Process to improve high performance capacitor properties in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process to improve high performance capacitor properties in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to improve high performance capacitor properties in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3665262