Programmable logic device with internal time-constant multiplexi

Details Programmable logic device with internal time-constant multiplexi Programmable logic device with internal time-constant multiplexi

1995-06-01

1997-04-15

Trans, Vincent N.

Boots, shoes, and leggings

364488, 326 41, 34082583, H03K 17693

Patent

active

056216505

ABSTRACT:
A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

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Electro/87 and Mini/Micro Northeast Conference Record, vol. 12, 1987, Los Angeles, pp. 19/4;1-9, XP002014072 Pardner Wynn: "Designing with Logic Cell Arrays", p. 4, left col., last paragraph, p. 5, left col., last paragraph, Figs. 1, 7-9.

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