Semiconductor memory device having memory cells similarly layout

Details Semiconductor memory device having memory cells similarly layout Semiconductor memory device having memory cells similarly layout

1998-05-20

2000-03-07

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257390, H07L 27108

Patent

active

060343842

ABSTRACT:
A semiconductor dynamic random access memory device includes plural memory cell arrays arranged in two columns, and the memory cell arrays of one column has memory cell sub-arrays and peripheral circuits such as sense amplifiers and sub-word line drivers arranged around the memory cell sub-arrays; the memory cells of the sub-arrays are arranged in a first pattern, and the peripheral circuits of adjacent sub-arrays are arranged in symmetry with respect to a line of symmetry perpendicular to the direction of the columns so as to increase a margin of alignment without sacrifice of simplicity of design work.

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patent: 5591995 (1997-01-01), Shaw
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Takanori Saeki et al., "A 2.5ns Clock Access 250MHz 256Mb SDRAM With a Synchronous Mirror Delay", IEEE International Solid-State Circuits Conference, 1996, pp. 374-375.

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