Semiconductor memory system and method for multi-sector...

Details Semiconductor memory system and method for multi-sector... Semiconductor memory system and method for multi-sector...

2006-10-31

2006-10-31

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S230080, C365S185290, C365S218000

Reexamination Certificate

active

07130240

ABSTRACT:
A semiconductor memory device is operable with a multi-sector erase mode for a multiplicity of memory chips, including a cell array, a register circuit containing information for a sector to be erased, an address clock driving circuit for contemporaneously generating an address clock signal from each memory chips, a counter for generating address signals in sequence, a core driver for executing an erase operation for the sector, and a control circuit thereof.

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