Jitter reduction

Details Jitter reduction Jitter reduction

2006-06-20

2006-06-20

Tran, Khai (Department: 2637)

Pulse or digital communications

Synchronizers

C375S356000, C375S371000, C375S373000, C375S377000, C327S141000, C327S261000, C370S503000, C714S700000

Reexamination Certificate

active

07065168

ABSTRACT:
Decoders process a digital input word to derive thermometer-coded signals for controlling one cell of an array of cells, commencing operation at the rising edge of a first clock signal. Each cell has a first latch clocked by a second clock signal, delayed by a preselected delay time Δ1relative to the first clock signal, and a second, transparent latch clocked by a third clock signal whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element used to delay the first clock signal by Δ1. The falling edge is affected by such jitter, but is prevented from feeding through to final outputs because the second latch is non-transparent at that falling edge.

REFERENCES:
patent: 4947171 (1990-08-01), Pfeifer et al.
patent: 5272729 (1993-12-01), Bechade et al.
patent: 5479455 (1995-12-01), Hata
patent: 2 215 925 (1989-09-01), None
patent: 2 333 171 (1999-07-01), None

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