Data receiving system robust against jitter of clock

Details Data receiving system robust against jitter of clock Data receiving system robust against jitter of clock

2006-02-07

2006-02-07

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000, C370S517000, C327S144000, C327S161000

Reexamination Certificate

active

06996201

ABSTRACT:
A plurality of delay circuits successively delay a received data. The received data and delayed data signals are sampled in response to both leading and trailing edges of a clock having a frequency substantially identical with that of a data transmission rate of the received data. When a sampling value having the same value V (V=1 or 0) appears continuously N times in the sampling operation of the received data101(where N is an even number), it is judged that a data of value V is continuously received (N/2) times.

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European Search Report dated May 26, 2004.

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