Register controlled delay locked loop with low power...

Details Register controlled delay locked loop with low power... Register controlled delay locked loop with low power...

2006-02-07

2006-02-07

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06995591

ABSTRACT:
The present invention relates to a digital delay locked loop (DLL) in DDR SDRAM (Double Data Rate Synchronous DRAM). The digital delay locked loop according to the present invention includes: first and second delay lines, each of which includes a plurality of delay groups, for delaying a source clock signal and a delay monitoring signal, wherein each of the delay groups include a plurality of programmable unit delayers; a delay model receiving an output signal of the second delay line for modeling a delay component of a clock signal path; a comparator for comparing a feedback clock signal from the delay model with a reference clock signal; a delay controller for controlling an amount of delay time of the first and second delay lines in response to a comparison result of the comparator; and first and second clock input controllers, which selectively provides the source clock signal and the delay monitoring clock signal to one of delay groups in the first and second delay lines, respectively, in response to output signals of the delay controller.

REFERENCES:
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patent: 6593786 (2003-07-01), Jung
patent: 6608514 (2003-08-01), Akita et al.
patent: 6768690 (2004-07-01), Kwon et al.
patent: 6822494 (2004-11-01), Kim

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