Low power serializer circuit and method

Coded data generation or conversion – Digital code to digital code converters – Serial to parallel

Reexamination Certificate

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C341S101000

Reexamination Certificate

active

07006021

ABSTRACT:
A serializer within, for example, a transceiver is provided having multiple stages of pipelined multiplexing cells. Each multiplexing cell may be substantially the same and each comprises no more than one latch. In some embodiments, each multiplexing cell includes a multiplexer comprising a pair of inputs and a single latch, which is coupled to one input of the multiplexer. No latches are coupled to the other input of the multiplexer. The serializer generally includes a plurality of stages. Each successive stage includes one-half the number of multiplexing cells included in the previous stage, and each successive stage is clocked by a clocking signal that transitions at twice the frequency of the previous stage clock signal.

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Lombaard, “Low-Power Pipelined ‘Ripple Architecture’ Serializer,” Cypress International Technical Conference, Jul. 2002, pp. 1-2.
Green et al., “OC-192 Transmitter in Standard 0.18 μm CMOS,” IEEE ISSCC 2002, Session 15, Gigabit Communications, ISSCC Visuals Supplement, pp. 198, 199, 469.
Cong et al., “A 10-Gb/s 16:1 Multiplexer and 10-GHz Clock Synthesizer in 0.25-μm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits, vol. 36, No. 12, Dec. 2001, pp. 1946-1953.
Andersson et al., “Silicon Bipolar Chipset for SONET/SDH 10 Gb/s Fiber-Optic Communication Links,” IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 210-218.

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