High-speed synchronous counters with reduced logic complexity

Details High-speed synchronous counters with reduced logic complexity High-speed synchronous counters with reduced logic complexity

2006-02-21

2006-02-21

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Including ring counter

C377S122000, C377S116000

Reexamination Certificate

active

07003067

ABSTRACT:
Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

REFERENCES:
patent: 3571573 (1971-03-01), Ott
patent: 6396312 (2002-05-01), Shepston et al.
M. Rafiquzzaman; “Fundamentals of Digital Logic and Microcomputer Design”; Copyright 1999 by Rafi Systems, Inc.; pp. 210-215.
Barry Wilkinson; “The Essence of Digital Design” Prentice Hall Europe 1998; pp. 120-130.
http:/www.eelab.usyd.edu.au/digital—tutorial/part2/register07.html; “Shift Register Counters”; 2 pages.

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