1975-07-14
1977-08-16
Wojciechowicz, Edward J.
357 51, 357 54, 357 90, H01L 2978, H01L 2702, H01L 2934
Patent
active
040429458
ABSTRACT:
An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.
REFERENCES:
patent: 3633078 (1972-01-01), Dill et al.
Lin Hung C.
White Marvin H.
Hinson J. B.
Westinghouse Electric Corporation
Wojciechowicz Edward J.
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