Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
2006-05-09
2006-05-09
Rodrigueg, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C711S151000, C370S220000
Reexamination Certificate
active
07043417
ABSTRACT:
In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.
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Beausoleil William F.
Cook R. Bryan
Ng Tak-kwong
Roth Helmut
Tannenbaum Peter
Craig Dwin M.
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
Rodrigueg Paul L.
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