Nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185120, C365S185130

Reexamination Certificate

active

07054195

ABSTRACT:
The number of electrons existing in a channel region within a NAND cell unit is reduced, and erroneous write-in characteristics are improved by the present invention. A nonvolatile semiconductor memory includes a control gate line drive circuit, which writes simultaneously in all memory cell transistors connected to a selected control gate line, performs write-in by maintaining a low channel voltage for a selected memory transistor in a selected memory cell unit when a plus voltage is applied to the selected control gate line, and restricts write-in utilizing a voltage self-boosted from the channel voltage for an unselected memory transistor.

REFERENCES:
patent: 6031764 (2000-02-01), Imamiya et al.
patent: 6049494 (2000-04-01), Sakui et al.
patent: 6064611 (2000-05-01), Tanaka et al.
patent: 2005/0105335 (2005-05-01), Sugimae et al.
K-D. Suh, et al., IEEE Journal of Solid-State Circuits, vol. 30, No. 11, pp. 1149-1156, “A 3.3 V 32 Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme”, Nov. 1995.

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