Retention register for system-transparent state retention

Details Retention register for system-transparent state retention Retention register for system-transparent state retention

2006-08-15

2006-08-15

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S206000, C327S208000

Reexamination Certificate

active

07091766

ABSTRACT:
State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vttransistors (M1, M2, M5and M6; M3, M4, M5and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.

REFERENCES:
patent: 6304122 (2001-10-01), Gregor et al.
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“Retention Register with Normal Functionality Independent of Retention Power Supply”, U.S. Appl. No. 10/613,271, Filed on Jul. 3, 2003.
S. Shigematsu, et al., “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,”IEEE Journal of Solid State Circuits, vol. 32, No. 6, pp. 861-869, Jun. 1997.

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