Non-volatile memory technology suitable for flash and byte...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185240, C365S185260

Reexamination Certificate

active

07088623

ABSTRACT:
The present invention provides a non-volatile memory cell structure suitable for the flash memory cell and EEPROM cell (electrically erasable programmable read only memory cell) to perform the byte programming and byte erasing operations. In the programming operation, a higher negative voltage applied to the drain region, such that the hot holes is generated to induce the hot electrons into the floating gate through the tunneling oxide layer in the lateral electrical field. In addition, the gate voltage is around the threshold voltage, which dependent on the integration circuit device design. Furthermore, the non-volatile memory cell utilized the channel Fowler-Nordheim tunneling for erasing operation. In order to perform the byte erasing operation, the drain junction used as an inhibition switch. Thus, the unselected cell in the same word line is inhibited by biasing the drain to ground. Therefore, the word lines of unselected cells are grounded.

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patent: 6556481 (2003-04-01), Hsu et al.
patent: 6731544 (2004-05-01), Han et al.

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