Wafer level packages for chips with sawn edge protection

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

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Details

C438S462000

Reexamination Certificate

active

07091062

ABSTRACT:
The invention relates to a wafer level package for chips with chip edge protection, comprising individual chips, which can in each case be mounted on a suitable carrier board, and to a method for producing such a wafer level package. Aspects of the invention can be achieved by the chip being thinned extremely from the back side and bonded onto a fiber reinforced synthetic resin sheet, forming a solidly bonded assembly that cannot come apart in the customary temperature range, and the edges of the assembly being at least partly coated with a polymer.

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patent: 101 64 494 (2003-07-01), None

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