Method of making semiconductor deivce using a conductive layer a

Details Method of making semiconductor deivce using a conductive layer a Method of making semiconductor deivce using a conductive layer a

1983-06-09

1985-09-17

Andrews, Melvyn J.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29590, 29591, 148DIG111, 148DIG141, 156643, 156653, 156657, 1566611, 357 59, 357 231, H01L 21283

Patent

active

045411662

ABSTRACT:
A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer. The first semiconductor region serves as either one of source and drain regions; that region of the semiconductor substrate underlying the conductive layer serves as a channel forming region; that region of the conductive layer facing the channel forming region serves as a gate electrode; and that region of the insulating layer underlying the gate electrode serves as a gate insulating layer.
The MIS FET can easily be combined with another MIS FET, a resistance element or capacitance element which is formed through utilization of the layer member of the former.

REFERENCES:
patent: 4356622 (1982-11-01), Widmann
patent: 4466172 (1984-08-01), Batra
patent: 4471522 (1984-09-01), Jambotkar

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