Multi-package stack module

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S723000, C361S803000

Reexamination Certificate

active

07061087

ABSTRACT:
A multi-package module comprises a plurality of stacked packages including an upper package and a lower package. Each package comprises a board having located on a first side thereof a chip installation area and a bump pad area; at least one chip disposed in the chip installation area; a plurality of redistribution patterns formed on the board and electrically connected to the chip; and a plurality of first bump pads formed in the bump pad area which are electrically connected to the redistribution patterns. The respective packages are electrically connected by connecting bump pads of the upper package to bump pads of the lower package. Further, the chip installation area of the upper and lower packages not being in vertical alignment with each other.

REFERENCES:
patent: 5598033 (1997-01-01), Behlen et al.
patent: 6014313 (2000-01-01), Hesselbom
patent: 6239496 (2001-05-01), Asada
patent: 6388333 (2002-05-01), Taniguchi et al.
patent: 6781241 (2004-08-01), Nishimura et al.
patent: 2001-118983 (2001-04-01), None
patent: 2002-55573 (2002-07-01), None
English Language of abstract for Korean Patent Publication No. 2002-55573, filed Jul. 9, 2002.
English Language of abstract for Japanese Patent Publication No. 2001-118983, filed Apr. 27, 2001.

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