Method, device and system for output impedance calibration...

Telephonic communications – Line equalization or impedance matching

Reexamination Certificate

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C379S399010, C379S402000

Reexamination Certificate

active

07031456

ABSTRACT:
A hybrid system with adjustable on-chip components and a method calibrating the same invariably maximizes hybrid performance despite of on- and off-chip component mismatches and imperfections. The hybrid system has a main DAC, a replica DAC, and three or four resistors. Both DACs are directly connected to digital data. An adjustable resistor is connected to the main DAC and is calibrated such that output impedance is automatically adjusted to match an off-chip load impedance Z. A replica DAC current K is calibrated for optimum DC matching in presence of Z. An adjustable capacitor C2is calibrated for slope-matching (bandwidth matching). If Z changes, the calibration procedure should be repeated for optimal performance. These three calibration mechanisms can be utilized individually or in combination. The present invention is compatible with both analog and digital echo-cancellers.

REFERENCES:
patent: 5329585 (1994-07-01), Susak et al.
patent: 6496988 (2002-12-01), Hammond
patent: 6628779 (2003-09-01), Pietrowiez
patent: 6687235 (2004-02-01), Chu
patent: 6704349 (2004-03-01), Masenten
patent: 2001/0036261 (2001-11-01), Prendergast et al.
patent: 2003/0099208 (2003-05-01), Graziano et al.
patent: 2004/0151238 (2004-08-01), Masenten
patent: 2004/0174990 (2004-09-01), Apfel
Moyal, M., Groepl, M., and Blon, T., “A 25-kft, 768-kb/s CMOS Analog Front End for Multiple-Bit-Rate DSL Transceiver,” IEEE Journal of Solid-State Circuits, vol. 34, No.12, Dec. 1999, pp. 1961-1972.
Tai-Cheng Lee and Behzad Razavi, A 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, p. 366.
Roo, P.; Sutardja, S.; Wei, S.; Aram, F.; Cheng, Y., “A CMOS Transceiver Analog Front-End for Gigabit Ethernet over CAT-5 Cables,” Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International, Feb. 5-7, 2001, pp. 310-311, 458.
Nauta, B.; Dijkstra, M.B., “Analog Line Driver with Adaptive Impedance Matching,” IEEE Journal of Solid-State Circuits, vol. 33, Issue: 12, Dec. 1998, pp. 1992-1998.

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