Semiconductor memory system including selection transistors

Static information storage and retrieval – Floating gate

Reexamination Certificate

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C365S185070, C365S185080

Reexamination Certificate

active

07023728

ABSTRACT:
A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively.Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively.The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

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patent: 5790466 (1998-08-01), Hotta
patent: 6284585 (2001-09-01), Camerlenghi et al.
patent: 6331947 (2001-12-01), Widdershoven et al.
patent: 6404678 (2002-06-01), Lin
patent: 0 601 207 (1994-06-01), None
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European Search Report for EP 02 42 5796 dated Apr. 9, 2003.

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